Publications and Presentations

• P. Häfliger, M. Mikkelsen, "In-pixel ADC architecture with hyperbolic
  compression HDR and CDS", submitted (Oct-2020) to IEEE ISCAS 2021

• B. S. Rikan, P. Häfliger, G. Cibrario, O. Billoint and M. Mouhdach, "Mixed Signal Circuit Design in a SinC Monolithic 3D Process", submitted Sep-2020 to IEEE TCAS-II.

• P. Häfliger, "Introduction : The 3D-MUSE project", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Dissemination Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• Camila Cavalcante , "3D Sequential Integration: towards analog on digital stacking", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Dissemination Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• Petros Sideris  , "Inter-tier coupling effects and shielding in Sequential 3D integration", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Dissemination Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• Mehdi Mouhdach, Olivier Billoint   , "Merging PDKs to build a Multi-Process Multi-Tier 3D design environment", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Dissemination Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• P. Häfliger, M. Mikkelsen, "Ultra dense 3D integrated circuits and pixel parallel processing image sensors", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Dissemination Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• Jean Michailos, "Image sensor hybrid bonding and sequential integration", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Disseminion Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• Arturo Prieto, "Design of Standard Cells with 3D Sequential Integration Technology for Multiply-Accumulate Operations", presented at the IEEE ESSCIRC/ESSDERC 2020 Educational Event Disseminion Workshop: "High Density 3D CMOS Mixed-Signal Opportunities".

• C. Fenouillet-Beranger et al., “First demonstration of low temperature (≤500°C) CMOS devices featuring functional RO and SRAM bitcells toward 3D VLSI integration”, 2020 Symposia on VLSI Technology and Circuits, June 2020.

• C. Cavalcante et al., “28nm FDSOI CMOS technology (FEOL and BEOL) thermal stability for 3D Sequential Integration: yield and reliability analysis”, 2020 Symposia on VLSI Technology and Circuits, June 2020

• C. Cavalcante, ‘Low Temperature High Voltage Analog Devices in a 3D Sequential Integration’, presented at the VLSI-TSA, 2020, p. Accepted for publication.C.
• T. A. Karatsori, ‘Statistical Characterization and Modelling of Gate-Induced Drain Leakage Variability in Advanced FDSOI Devices’, presented at the IEEE S3S conference, San Jose, CA, USA, 2019.
• T. A. Karatsori, K. Bennamane, and G. Ghibaudo, ‘Novel on-resistance based methodology for MOSFET electrical characterization’, Solid-State Electron., p. 107722, Nov. 2019.
• P. Batude, "3D sequential integration" Tutorial, IEDM, San Francisco, USA, Dec. 2019
• O. Billoint et al., “Merging PDKs to build a design environment for 3D circuits: methodology, challenges and limitations”, 3DIC’2019, Sendai, Japan, Oct. 2019.
• P. Häfliger. Ultra dense 3D integrated circuits and pixel parallel processing image sensors, Impact Breakfast, Oslo, Norway, Sep. 2019
• C. Cavalcante et al., Bottom Tier High Voltage Device Thermal Stability in 3D Sequential Integration for More than Moore Applications, SSDM’2019, Nagoya, Japan, Sept. 2019.
• P. Vivet etal. Advanced 3D Technologies and Architectures for 3D Smart Image Sensors, technology perspectives and associated design methodology challenges. In DATE - Special session '3D Sensor ­ Hardware to Application', Florence, Italy, March 2019.
• P. Vivet etal. Monolithic 3D: an alternative to advanced CMOS scaling, technology perspectives and associated design methodology challenges. In ICECS, Bordeaux, France, December 2018.
• L. Brunet etal. Breakthroughs in 3D sequential technology. In IEDM, San Francisco, USA, December 2018.
• S. Thuriès etal. 3DVLSI CoolCube MPW & design roadmap. In SES - 3DVLSI Open Workshop, San Francisco, USA, October 2018.
• S. Chéramy etal. 3DVLSI, technology and application. In S3S, San Francisco, USA, October 2018.
• P. Häfliger. CMOS sequential 3d integration for mixed-signal 'systems-in- cube'. In Korea-EU WS on low-power nanoelectronics, Seoul, South Korea, September 2018.
• S. Thuriès etal. 3D sequential integration: overview of 65 nm on 28 nm fdsoi mpw architecture and design contributions. In D43D Workshop, Grenoble, France, July 2018.
• P. Batude etal. 3D sequential integration: review of opportunities and technology updates. In D43D Workshop, Grenoble, France, July 2018.
• F. Andrieu etal. A review on opportunities brought by 3d-monolithic integration for CMOS device and digital circuit. In ICIDT, Otranto, Italy, June 2018.
• P. Häfliger. CMOS sequential 3d integration for mixed-signal 'systems-in- cube'. In The Nano Network annual workshop, Tjøme, Norway, June 2018.
• L. Brunet etal. 3D monolithic integration. In ECS, Seattle, USA, May 2018.

A Sequential 3D Review Just Predating the Project Start

• P. Batude etal. 3D sequential integration: Application-driven technological achievements and guidelines. In IEDM, San Francisco, USA, December 2017.