3D-MUSE Key Technology: Sequential 3D Integration
Partner CEA/LETI in collaboration with partners ST Microelectronics and INP Grenoble/IMEP is developing 3D sequential integration in state of the art 28nm CMOS technology, enabling 3D integrated circuit designs where the vertical inter-tier via density is of the same order of magnitude as the horizontal wire density. In 3D-MUSE they are extending their CoolCube™ technology specifically for mixed signal process options.
3D-MUSE Mixed-Signal 'Systems-in-a-Cube'
3D-MUSE wants to spearhead the progression from what we shall refer to as 'systems-in-stack' to true 'systems-in-cube' (SinC) that monolithic/sequential 3D integration will enable. We define the former as a 3D system that is characterized by locating functional blocks within a single plane in the (typically parallel/wafer-bonding) 3D integration stack, while the latter makes use of the full emancipation of the interconnect density in the third dimension of sequential 3D integration and rather implements functional blocks in a volume comprising multiple tiers.
System-in-Stack Design in Established 3D Integration
Established 3D integration today has a connection density in the vertical between tiers that is one or several orders of magnitude smaller than the connection density in the horizontal in 2D CMOS technology. Thus, large electronic system architectures do not yet freely use the 3D volume since every vertical connection still comes at a significant cost, i.e. layout space occupied by the TSV. Consequently, these architectures are characterized by (in particular mixed signal architectures):
- Functional (mixed signal) blocks are restricted to one tier;
- Mixed signal options required for every tier;
- Only a few large through silicon vias (TSV) connecting tiers in the z-direction.
System-in-Cube Design in Sequential 3D Integration
In contrast, sequential 3D integration paves the way for a vertical connection density on par with the horizontal connection density. Thus, system architectures can now fully embrace placement of each individual system component in a volume and have characteristics such as (again particularly mixed signal architectures):
- Functional (mixed signal) blocks spread in a volume.
- Specialized tiers for a single signal domain.
- Vertical inter-tier connection density on par with horizontal tier internal 2D connection density.
Partners University of Oslo, IDEAS AS, and Lund University are exploring the new trade-offs and performance enhancements of System-in-Cube (SinC) architectures that the full emancipation of the 3rd dimension in integrated circuit design will enable for a number of IoT and sensor-node applications. In particular we are looking into 'Smart Sensor Interfaces' (SSI), i.e. mixed signal designs connecting the real world with electronic devices.
3D-MUSE Smart Sensor Interfaces
The IoT is composed of connected devices that are characterized by their interaction with the environment via a plethora of sensors and actuators. The trend goes to ever more complex interactions and thus an increase in the number of different sensors integrated in the same product, which in turn requires the processing capability to handle all of those sensors. At the same time those systems are expected to still perform on an ever lower power budget, preferably so low as to be able to operate purely on power scavenging. And of course the cost needs to be moderate too. The electronics at the heart of such a system needs to be mixed-signal electronics that interfaces to the analog sensors and actuators, but can also provide the necessary digital processing power. We refer to such systems as Smart Sensor Interfaces (SSI).
We shall demonstrate System-in_Cube (SinC) implementations of SSIs by conceiving novel architectures for micro circuits in a volume in a (for now 2-tier) 3D sequential integration process. In particular, we have identified mixed-signal circuits as, on one hand, a major bottleneck for functional performance scaling of sensor nodes and smart sensors in the IoT and cyberphysical systems, and on the other hand, excellent candidates for beneficial trade-offs when implemented asSinC in sequential 3D integration technology with using two specialize tiers providing specific CMOS process options, one for analog devices and the other for optimal digital designs. We call such a 3D technology 'multi-process' sequential 3D integration, hence the project acronym '3D-MUSE'.